Best Talent Reach (BTR) Design Verification Engineers at Skalen Semi

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DESIGN VERIFICATION ENGINEERS @ SKALEN SEMI

0 Negotiable or Not Mentioned India 56 days ago skalensemi.com 2275 Views

Skalen Semi is currently seeking experienced Design Verification Engineers with a career background spanning 5 to 15 years. This role involves working within a versatile environment ranging from large IT design services to innovative start-up design projects, offering a unique opportunity for professional growth in the semiconductor industry. The successful candidates will be tasked with high-level verification responsibilities, focusing on System-on-Chip (SoC) and Intellectual Property (IP) blocks to ensure high-quality product delivery. Possible work locations for these positions include Bangalore, Hyderabad, and Noida, allowing for flexibility within India's tech hubs. The role demands expertise in advanced verification methodologies and tools. You will be expected to drive verification strategy, execute test plans, and ensure comprehensive coverage closure across various complex digital designs. Collaboration with cross-functional teams is essential to meet project milestones and technical specifications. Joining Skalen Semi means becoming part of a forward-thinking team dedicated to digital transformation and innovation in chip design.

Key Requirements

Must have between 5 and 15 years of relevant experience in Design Verification. Extensive proficiency in SystemVerilog and UVM (Universal Verification Methodology) is required. Proven track record in Subsystem, SoC, or IP level verification processes. Hands-on experience with high-speed protocols such as PCIe, CXL, DDR, or USB. In-depth knowledge of AMBA bus protocols including AXI, AHB, and APB. Experience in implementing low power verification strategies and methodologies. Strong skills in debugging complex designs and achieving coverage closure. Familiarity with regression management and automation within verification environments. Proficiency in using EDA tools from major vendors like Synopsys, Cadence, or Siemens. A solid educational background in Electronics Engineering, VLSI, or a related field.

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RTL DESIGN ENGINEER @ SKALEN SEMI

0 Negotiable or Not Mentioned India 60 days ago skalensemi.com 571 Views

Skalen Semi is seeking highly experienced and skilled RTL Design Engineers to join our dynamic team. This critical role involves working on cutting-edge projects for a diverse clientele, including large IT firms, design services companies, and fast-growing mid-sized startups. Candidates must possess significant experience, ranging from 5 to 15 years, in the field of RTL design and microarchitecture development. The primary responsibilities will e

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DFT ENGINEERS @ SKALEN SEMI

0 Negotiable or Not Mentioned India 58 days ago skalensemi.com 560 Views

Skalen Semi is looking for experienced DFT Engineers to join their dynamic team. This role is ideal for professionals with 5 to 15 years of experience in the semiconductor industry, working with large IT and design services as well as fast-growing mid-sized and start-up design services. The successful candidates will be responsible for various aspects of Design for Testability, ensuring high-quality silicon production and testing efficiency. The

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STA AND SYNTHESIS ENGINEERS @ SKALEN SEMI

0 Negotiable or Not Mentioned India 58 days ago skalensemi.com 560 Views

Skalen Semi is actively seeking experienced STA and Synthesis Engineers to join their team. This role involves providing high-end design services to a range of clients, from large IT corporations to fast-growing mid-sized firms and innovative startups. Candidates will be responsible for critical aspects of the silicon development cycle, specifically focusing on Static Timing Analysis (STA), timing closure, and logic synthesis for complex ASIC and

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PHYSICAL DESIGN ENGINEER @ SKALEN SEMI

0 Negotiable or Not Mentioned India, Multiple Locations 60 days ago skalensemi.com 572 Views

Skalen Semi is actively seeking highly skilled and experienced Physical Design Engineers to join their growing team. This role supports various clients, ranging from large established IT and design services to fast-growing mid-sized and start-up design companies. Successful candidates will be responsible for executing the complete physical design flow from RTL to GDS, ensuring high performance, low power, and robust design quality across various

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DESIGN VERIFICATION (DV) ENGINEERS @ KARASHATECH

0 Negotiable or Not Mentioned India, Hyderabad 11 days ago karashatech.com 426 Views

KarashaTech is seeking highly skilled and experienced Design Verification (DV) Engineers to join our rapidly growing technical team in Hyderabad. In this role, you will be responsible for the verification of complex integrated circuits, ensuring that designs meet functional requirements and power specifications. You will work closely with design teams to define verification strategies and develop robust testbenches that leverage advanced industry methodologies. This is an excellent opportunity for a professional looking to work on cutting-edge semiconductor projects within a collaborative and innovative environment.The successful candidate will demonstrate a deep understanding of the full verification lifecycle, from planning to coverage closure. You will be expected to handle power-aware simulations and debug intricate issues across RTL and UPF models. With a requirement for at least five years of experience, we are looking for engineers who can hit the ground running and contribute to our high-standards of silicon quality. Candidates with a short notice period are highly preferred to meet our current project timelines.

Key Requirements

Minimum of 5 years of professional experience in Design Verification. Strong hands-on experience with SystemVerilog for verification. Advanced proficiency in Universal Verification Methodology (UVM). Solid understanding of Unified Power Format (UPF) and Power Intent Modeling. Proven experience conducting Power-Aware Simulations. In-depth knowledge of Power Domains and Power States. Familiarity with Isolation, Retention, and Level Shifters within designs. Understanding of the interactions between Reset and Power states. Strong debugging skills across RTL, UPF, and various Testbench environments. Ability to join within a short notice period of approximately 15 days.

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ANALOG LAYOUT ENGINEER @ SKALEN SEMI

0 Negotiable or Not Mentioned India 61 days ago skalensemi.com 576 Views

Skalen Semi is actively seeking highly experienced Analog Layout Engineers (AMS Layout Engineers) to join our team. We are partnering with large IT and design services firms, as well as fast-growing mid-sized and startup design services companies. This crucial role targets candidates with substantial expertise, requiring 5 to 15 years of relevant industry experience. Successful candidates will be responsible for performing complex analog/mixed-si

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RTL DESIGN ENGINEER @ TIMES SEMICONDUCTORS

0 Negotiable or Not Mentioned India 11 days ago GMAIL.COM 867 Views

Times Semiconductors is seeking talented RTL Design Engineers to join our expanding team in India. In this role, you will play a pivotal part in designing and developing advanced semiconductor systems, focusing on ASIC and SoC innovation. You will work alongside industry experts to push the boundaries of what is possible in VLSI design and microelectronics.

Candidates can be based in several key tech hubs in India, including Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. Whether you are a fresh graduate or an experienced professional, we offer a dynamic platform for career advancement and technical skill development. Eligibility includes B.E/B.Tech or M.E/M.Tech graduates from the batches of 2012 through 2026.

Key Requirements

Bachelor's or Master's degree in ECE, EEE, or related engineering fields. Graduation year between 2012 and 2026. Strong proficiency in Verilog or SystemVerilog for hardware description. Knowledge of SoC integration processes and methodologies. Experience with scripting languages such as Python, TCL, or Perl. Familiarity with industry-standard EDA tools like VCS, Xcelium, or Questa. Solid understanding of digital logic design and computer architecture. Ability to work in a fast-paced environment on complex ASIC projects. Excellent analytical and problem-solving skills for debugging design issues. Strong communication skills for collaborating with global engineering teams.

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NPU PERFORMANCE VERIFICATION AND POWER MODELING LEAD @ QUALCOMM

0 Negotiable or Not Mentioned India, Hyderabad 57 days ago qti.qualcomm.com 559 Views

Qualcomm is seeking a highly skilled and experienced engineer to join the NPU team, focusing on performance verification and power modeling. This role is pivotal for the development of complex, proprietary DSP IP that forms the core of Qualcomm's multi-tier SoC roadmap. The successful candidate will bring between 12 and 18 years of industry experience to the DSP design team, ensuring the delivery of high-performance cores optimized for the mobile

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DDR VERIFICATION ENGINEER @ GSVR TALENT SOLUTIONS PVT LTD

0 Negotiable or Not Mentioned India 18 days ago gsvrtalent.com 990 Views

GSVR Talent Solutions Pvt Ltd is hiring experienced DDR Verification Engineers to join their high-performance semiconductor team. This role involves working on cutting-edge technology including next-generation AI chips and high-speed memory interfaces. The chosen candidate will be responsible for the verification of DDR3, DDR4, DDR5, and LPDDR4/LPDDR5 controllers, ensuring that every memory transaction behaves exactly as expected before silicon production. You will develop UVM-based verification environments using DDR VIPs and work closely with senior VLSI engineering teams.

In this position, you will create and debug complex memory traffic scenarios and ensure strict protocol compliance through functional coverage closure. The role requires a strong debugging and analytical mindset to solve intricate hardware validation challenges. By joining this project, you will contribute to the development of high-performance computing systems and collaborate with experts in the VLSI industry to deliver reliable hardware solutions for modern technology infrastructures.

Key Requirements

At least 4 years of professional experience in Design Verification within the VLSI or semiconductor industry. Strong technical knowledge of DDR protocols including DDR3, DDR4, and DDR5. Hands-on expertise with LPDDR4 and LPDDR5 memory architectures and controllers. Proven experience in developing and maintaining UVM-based (Universal Verification Methodology) environments. Advanced proficiency in using SystemVerilog for hardware verification tasks. Direct experience working with DDR Verification IPs (VIPs) and associated debugging tools. Ability to create, simulate, and debug complex memory traffic scenarios for validation. Demonstrated ability to ensure protocol compliance and achieve functional coverage closure. A strong debugging and analytical mindset to resolve architectural and functional issues. Ability to collaborate effectively with cross-functional engineering teams on high-performance computing projects.

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DESIGN VERIFICATION ENGINEER @ TIMES SEMICONDUCTORS

0 Negotiable or Not Mentioned India 11 days ago GMAIL.COM 501 Views

Times Semiconductors is hiring Design Verification Engineers to join our prominent engineering teams across India. You will be responsible for creating robust verification strategies for complex SoC and ASIC designs, utilizing UVM and SystemVerilog. This position offers the chance to work on high-impact projects that define the future of the global semiconductor industry.

Work locations include top Indian cities like Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. We welcome applications from engineers at all stages of their careers who are passionate about semiconductor innovation. This role requires a strong academic background in electronics and communication or electrical engineering and a dedication to high-quality design verification standards.

Key Requirements

B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields. Graduation date falling between 2012 and 2026. Expertise in SystemVerilog and UVM (Universal Verification Methodology). Experience developing testbenches and verification environments from scratch. Proficiency in scripting with Python, Perl, or TCL. Hands-on experience with simulation tools like VCS, Xcelium, or Questa. In-depth knowledge of coverage-driven verification and assertion-based verification. Strong debugging skills and ability to analyze complex RTL code. Knowledge of computer architecture and digital logic design fundamentals. Ability to work effectively within a cross-functional team environment.

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ANALOG IC DESIGN ENGINEER @ SKALEN SEMI

0 Negotiable or Not Mentioned India 59 days ago skalensemi.com 565 Views

Skalen Semi is actively seeking an experienced Analog IC Design Engineer to join our growing team. This role supports both large IT and design services clients, as well as fast-growing mid-sized and start-up design services firms. Successful candidates will be instrumental in the design, simulation, and verification of complex analog and mixed-signal integrated circuits. The ideal candidate possesses between 5 and 15 years of relevant industry ex

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DV-GLS ENGINEER @ GSVR TALENT SOLUTIONS PVT LTD

0 Negotiable or Not Mentioned India 62 days ago gsvrtalent.com 579 Views

GSVR Talent Solutions is actively seeking a highly skilled Design Verification Engineer specializing in Gate-Level Simulation (GLS). This role is centered within the rapidly evolving semiconductor industry, requiring candidates who possess a minimum of four years of relevant experience in VLSI verification. The successful applicant will be crucial in ensuring the robustness and accuracy of complex digital designs through rigorous testing and simu

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RTL DESIGN ENGINEER @ SKALEN SEMI

0 Negotiable or Not Mentioned India 28 days ago skalensemi.com 1176 Views

Skalen Semi is seeking an experienced RTL Design Engineer to join a dynamic team working with global design services powerhouses. The role involves deep involvement in high-performance and low-power RTL development, microarchitecture definition, and SoC architecture design. You will be responsible for creating synthesis-ready RTL, managing timing closure (STA), and ensuring logical equivalence using tools such as Conformal or Formality.

This position is available in both Bangalore and Hyderabad. Candidates must have significant experience in the semiconductor industry, specifically within ASIC and chip design environments. Please note that this is a senior-level position requiring 6 to 12 years of relevant experience; applications from freshers or interns are not being accepted at this time.

Key Requirements

6 to 12 years of professional experience in RTL Design and Development. Proven expertise in Microarchitecture and SoC Architecture design. Proficiency in Hardware Description Languages (HDL) like SystemVerilog and Verilog. Experience in IP Design and Subsystem Design for high-performance systems. Solid understanding of Low Power RTL design and Clocking Architecture. Familiarity with Pipeline Design and Bus/Interconnect architectures. Demonstrated ability to deliver Synthesis-Ready RTL and achieve Timing Closure (STA). Hands-on experience with LEC tools such as Conformal or Formality. Knowledge of DFT-ready RTL design and implementation best practices. Strong background in ASIC design flows and the semiconductor industry.

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STA AND SYNTHESIS(LEC) ENGINEERS @ SKALEN SEMI

0 Negotiable or Not Mentioned India 31 days ago skalensemi.com 1088 Views

Skalen Semi is looking to recruit highly skilled STA and Synthesis(LEC) Engineers with a minimum of 6 to 12 years of experience. These positions are open for candidates who have previously worked with global design services powerhouses and are proficient in the semiconductor field. The primary work locations for these roles are Bangalore and Hyderabad, where engineers will tackle complex design challenges. Candidates will be expected to work within a fast-paced environment and deliver high-quality results for our global clients in the design services industry. Responsibilities include performing Static Timing Analysis, Synthesis, and Logic Equivalence Checks. Candidates should be well-versed in tools such as PrimeTime, Tempus, DesignCompiler, and Genus. Knowledge of timing closure, IR drop analysis, and RTL2Gates processes is crucial for success in this role. The opportunity involves working on advanced nodes and contributing to the development of cutting-edge SoC and ASIC designs. Successful hires will collaborate with multi-disciplinary teams to ensure hardware performance meets stringent design goals and timing requirements.

Key Requirements

Minimum 6 to 12 years of experience in VLSI or semiconductor design. In-depth knowledge of Static Timing Analysis (STA) and timing closure. Proficiency in Synthesis and Logic Equivalence Check (LEC) workflows. Experience with industry-standard tools like PrimeTime or Tempus. Hands-on experience with RTL2Gates, DesignCompiler, or Genus. Understanding of MMMC (Multi-Mode Multi-Corner) analysis and SDF. Knowledge of IR Drop and EM Analysis for integrated circuits. Experience with advanced technology nodes (e.g., 7nm, 5nm). Ability to perform Clock Tree Analysis (CTS) and Power Optimization. Strong technical background in ASIC and SoC design methodologies.

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PHYSICAL DESIGN ENGINEERS (3 POSITIONS) @ SKALENSEMI

0 Negotiable or Not Mentioned India 14 days ago skalensemi.com 683 Views

SkalenSemi is seeking experienced Physical Design Engineers to join our dynamic team in India. This role is crucial for our high-performance chip design projects, focusing on advanced technology nodes and complex integrated circuits. Candidates will be responsible for the complete physical design flow, ensuring high-quality netlist-to-GDSII implementation while meeting stringent power, performance, and area goals. The available work locations for these positions include Bangalore and Pune, operating under an onsite work model.

The ideal candidate will have between 6 and 12 years of relevant industry experience and a strong background in VLSI design. Key responsibilities include managing placement and routing (PnR), performing clock tree synthesis (CTS), and conducting final sign-off procedures using industry-standard verification tools like Calibre. We are looking for individuals with a proven track record in ASIC design and chip implementation who are ready to contribute to cutting-edge technology developments. There are currently 3 open positions available for this role.

Key Requirements

Minimum 6 to 12 years of professional experience in Physical Design. Strong hands-on expertise in the entire Physical Design flow from netlist to GDSII. Extensive experience with sign-off processes including timing, power, and physical verification. Proficiency in Placement and Routing (PnR) techniques and industry-standard tools. Demonstrated expertise in Clock Tree Synthesis (CTS) for high-frequency designs. Practical experience using Calibre for DRC, LVS, and Antenna checks. Solid understanding of ASIC Design methodologies and chip architecture. Proven track record in Chip Design and implementation on advanced process nodes. Ability to work effectively in an onsite environment in Bangalore or Pune. Excellent technical problem-solving skills and the ability to work in a collaborative team environment.

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EXPERIENCED ENGINEERING TEAM LEAD @ SILICONUS TECHNOLOGIES

0 Negotiable or Not Mentioned India 53 days ago siliconus.com 537 Views

SiliconuS Technologies is currently seeking highly skilled and experienced professionals with 5 to 10 years of expertise to join our dynamic and growing team. This role is designed for individuals who are ready to transition into a leadership position or are already successfully leading engineering teams. We are looking for candidates who bring deep technical knowledge and a passion for innovation to help drive our company's mission forward in th

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ELECTRICAL ENGINEERING POD LEAD @ E-SOLUTIONS INC

0 Negotiable or Not Mentioned India, Remote 16 days ago e-solutionsinc.com 796 Views

This is a specialized remote opportunity for an Electrical Engineering Pod Lead to join a dynamic project for a duration of 22 weeks. The role requires a high level of technical expertise, necessitating a Master's degree or PhD and at least five years of deep hands-on electrical engineering design experience. As a Pod Lead, you will be responsible for owning designs from the initial specification phase through to validated implementation, providing technical leadership and team coordination to ensure project milestones are met effectively within the PST overlap hours.

Candidates must demonstrate advanced proficiency in Python for scripting and automation, alongside hands-on experience with Docker for managing containerized environments. Proficiency in at least one major cloud platform and various open-source EE simulation tools is required. You must have deep expertise in specialized subdomains such as Analog/Mixed-Signal IC Design, Power Electronics, RF Engineering, or Embedded Systems. The role demands a commitment of at least 30 to 40 hours per week, with a critical requirement for a 4-hour daily overlap with Pacific Standard Time.

Key Requirements

Master's degree or PhD in Electrical Engineering or a closely related field. Minimum 5 years of hands-on electrical engineering design experience. Proven track record of owning designs from specification through validated implementation. At least 1–2 years of experience in a technical lead, senior engineer, or team coordination role. Proficiency with Python for scripting, automation, and simulation workflows. Hands-on experience with Docker, including building images and managing containerized environments. Familiarity with cloud platforms such as AWS, GCP, or Azure for running workloads and monitoring jobs. Proficiency with open-source EE simulation tools like ngspice, PySpice, or OpenEMS. Deep expertise in Analog/Mixed-Signal IC Design or Power Electronics. Strong understanding of RF/Microwave Engineering or Digital Systems/FPGA design. Ability to work a minimum of 30-40 hours per week with a 4-hour PST overlap.

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SENIOR STA DESIGNER @ TECHEDGE SOLUTION

0 Negotiable or Not Mentioned India 20 days ago techedge-solution.com 575 Views

TechEdge Solution is seeking experienced professionals for the role of Senior Designer (STA). This position is ideal for candidates with over 7 years of expertise in VLSI and Physical Design, specifically focusing on timing analysis and design methodologies. The role involves working on high-stakes projects where you will ensure high-quality, consistent, and user-friendly design outputs. We are specifically looking for immediate joiners or those with a notice period of up to 30 days to join our dynamic engineering team.

Key responsibilities include collaborating with various stakeholders to understand complex design requirements, developing prototypes, and validating design concepts. You will work closely with cross-functional teams including Development, QA, and Product to ensure project success. Additionally, as a Senior Designer, you will be expected to mentor junior team members and provide technical leadership. Possible work locations for this role within India include Bangalore, Hyderabad, Chennai, and Noida. Preferred skills include familiarity with UX principles and design tools like Figma or Adobe XD to enhance cross-disciplinary collaboration.

Key Requirements

Strong experience in Static Timing Analysis (STA) Expertise in Constraint Development and TCL Scripting Good understanding of Synthesis (Syn) and APR (Place and Route) Proven experience in Timing Closure and Physical Design At least 7 years of relevant industry experience for Bangalore, Hyderabad, Chennai, or Noida locations Minimum of 15 years of experience specifically for senior-level placement in Bangalore Ability to collaborate with stakeholders to understand design requirements Experience developing prototypes and validating design concepts Capability to work closely with cross-functional teams including Dev, QA, and Product Strong mentorship skills for guiding junior team members

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PHYSICAL DESIGN ENGINEERS (3 POSITIONS) @ SKALENSEMI

0 Negotiable or Not Mentioned India 13 days ago skalensemi.com 658 Views

SkalenSemi is seeking experienced Physical Design Engineers for three open positions to join our team in India. This role requires individuals with a strong background in the full physical design cycle, from floorplanning to sign-off. Candidates will be expected to work on-site at our facilities in either Bangalore or Pune, contributing to cutting-edge ASIC and chip design projects. The work model is strictly onsite, ensuring close collaboration with our technical teams in these key technology hubs.

The successful candidates will have between 6 to 12 years of relevant industry experience in the semiconductor field. Key responsibilities include handling complex physical design tasks such as Place and Route (PnR), Clock Tree Synthesis (CTS), and sign-off verification using industry-standard tools like Calibre. A robust understanding of VLSI design and the ability to ensure high-quality design outcomes are essential for this position. This is an excellent opportunity to grow within a dynamic technical environment focused on semiconductor innovation and high-performance chip design.

Key Requirements

6-12 years of professional experience in Physical Design. Strong hands-on experience in Physical Design flow and sign-off processes. Proficiency in Place and Route (PnR) methodologies. In-depth knowledge and experience with Clock Tree Synthesis (CTS). Hands-on expertise with physical verification tools such as Calibre. Strong background in ASIC Design and VLSI technologies. Ability to work onsite at office locations in Bangalore or Pune. Experience with Static Timing Analysis (STA) and timing closure. Knowledge of sub-micron technology nodes (e.g., 7nm, 5nm). Familiarity with industry-standard EDA tools for physical implementation.

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CYBER SECURITY LEADERS (SALES / CONSULTING / PARTNERSHIP MANAGERS) @ AURISEG

0 Negotiable or Not Mentioned India 26 days ago auriseg.com 1477 Views

Auriseg is looking for experienced professionals in the Cyber Security domain to join their growing team as part of a global expansion initiative. The company is seeking candidates for multiple leadership roles including Sales Consultants, Business Development Managers, Consulting Managers specializing in Cyber Security Advisory & Risk, and Partnership & Channel Managers. Possible work locations within India include Bengaluru, Mumbai, Hyderabad, and Delhi. This is an opportunity to work with a forward-thinking global firm on cutting-edge security solutions and strategic alliances.

The ideal candidate will possess a minimum of five years of professional experience in the cybersecurity industry. Applicants should have a deep understanding of Cyber Security Sales, Strategic Partnerships, and technical solutions including VAPT, Red Teaming, SOC, Cloud Security, and GRC. Strong communication skills and a track record of driving business growth in high-stakes environments are essential for these positions. Join Auriseg to help shape the future of information security globally.

Key Requirements

Minimum 5 years of professional experience in the Cyber Security domain. Proven expertise in Cyber Security Sales and Consulting strategies. Demonstrated experience in managing Strategic Partnerships and Alliances. In-depth knowledge of VAPT (Vulnerability Assessment and Penetration Testing). Experience with Red Teaming and Security Operations Center (SOC) environments. Proficiency in Cloud Security solutions and GRC (Governance, Risk, and Compliance). Strong background in Business Development and Channel Management. Excellent analytical and problem-solving skills related to cyber threats. Ability to lead teams and manage complex security advisory projects. Strong networking and interpersonal communication skills.

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ASSOCIATE / SENIOR ASSOCIATE / PROJECT LEADER / MANAGER – MMX @ AXTRIA

0 Negotiable or Not Mentioned India 11 days ago axtria.com 347 Views

Axtria is expanding its Market Mix (MMx) Analytics team and is looking for high-impact analytics professionals passionate about the pharmaceutical and life sciences sector. As an integral part of the team, you will be responsible for building and leading Market Mix and Promotion Response models that drive strategic decisions for global clients. This role involves deep collaboration with international stakeholders and delivering high-quality, actionable insights through advanced analytics and data science methodologies. Candidates will work on cutting-edge AI/ML-driven analytics platforms and have the opportunity for continuous learning through the Axtria Institute.

The role also involves mentoring junior analysts and contributing to the overall growth of Axtria’s analytics capabilities in a transparent and collaborative culture. Possible work locations for this role include Gurgaon, Bangalore, Noida, Pune, and Hyderabad. At Axtria, we prioritize high-impact analytical work that directly influences pharmaceutical commercial excellence and marketing efficiency. You will be expected to utilize your expertise in Python or R and statistical modeling to provide best-in-class results for our partners. This is a unique opportunity to grow professionally within a supportive and innovative environment focused on health and life sciences.

Key Requirements

Minimum 2–6 years of experience in Marketing Analytics. At least 2 years of hands-on experience with MMx, PRM, or Test & Control models. Proficiency in Python or R programming for data analysis. Strong foundations in statistics and statistical modeling. Solid understanding of Machine Learning (ML) techniques. Experience in Pharma or Life Sciences industry is preferred. Proven ability to build and lead Market Mix and Promotion Response models. Experience in partnering with global and client stakeholders for delivery. Ability to deliver client-ready analytics and actionable insights. Experience in mentoring junior analysts and contributing to analytics platforms.

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AUTOMATION DEVELOPMENT ENGINEER (MSSP ENGINEERING) @ NTECH IT SOLUTIONS

0 Negotiable or Not Mentioned India, Hyderabad 57 days ago nTechitsolutions.in 556 Views

nTech IT Solutions is seeking a dedicated Automation Development Engineer to join our MSSP Engineering team in Hyderabad. This position is a 100% onsite role, operating on an afternoon or late afternoon shift schedule. The role is initially a contract position lasting 4 to 5 months, with a strong potential for full-time conversion based on the candidate's performance and professional attitude. The successful candidate will be passionate about bui

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AUTOMATION TEST ENGINEER @ SRS CONSULTING INC

0 Negotiable or Not Mentioned India, Hyderabad 57 days ago srsconsultinginc.com 555 Views

SRS Consulting Inc is looking for a talented Automation Test Engineer to join our dynamic team in Hyderabad. In this role, you will be responsible for ensuring the high quality of our web and mobile applications through rigorous automated testing. You will work closely with the development team to integrate testing into the CI/CD pipeline, ensuring that every release meets our high standards of performance and reliability. The ideal candidate sho

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SENIOR DEVELOPER (1 POSITION) @ ADBORN SOLUTIONS

0 Negotiable or Not Mentioned India 55 days ago adbornsolutions.com 547 Views

Adborn Solutions is currently seeking a highly skilled and experienced Senior Developer to join their esteemed client's team. This role is designed for a self-driven technologist with a passion for writing great code and a strong command over modern web technologies. The ideal candidate will be hands-on with full-stack development, capable of writing scalable, maintainable code, and contributing to architectural decisions that drive business impa

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SENIOR DEVELOPER (3 POSITIONS) @ OSSS CONSULTING SERVICES INDIA PVT. LTD

0 Negotiable or Not Mentioned India 55 days ago MINDTECHDIGITAL.COM 546 Views

OSSS Consulting Services India Pvt. Ltd is currently seeking an experienced Senior Developer to join their esteemed client's team. This role is designed for a technical expert with approximately 15 years of experience who excels at building scalable, high-performance backend systems. You will be responsible for designing robust and maintainable architectures, collaborating across functional teams, and ensuring the overall security and reliability

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SQL AND AWS SCRIPTING PROFESSIONAL @ UST

0 Negotiable or Not Mentioned India, Hyderabad 55 days ago ust.com 546 Views

UST is seeking highly skilled professionals for the role of SQL and AWS Scripting Professional to join our dynamic team in Hyderabad. In this role, you will be responsible for managing and optimizing complex database environments, leveraging AWS services like Aurora and utilizing Terraform for infrastructure management. You will play a critical role in ensuring database performance and reliability, while using scripting languages like Python and

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BACKEND DEVELOPER LEAD @ TALENT WING CONSULTANTS

0 Negotiable or Not Mentioned India 53 days ago talent-wing.com 535 Views

Talent Wing Consultants is urgently hiring a Backend Developer Lead to oversee complex technical projects and lead a team of talented software engineers. This role requires a seasoned professional with a deep understanding of backend systems, architectural design, and modern software development practices. The successful candidate will be instrumental in building scalable, robust systems that support high-performance applications and drive techno

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KUBERNETES PLATFORM TECHNICAL LEAD @ HYPTECHIE

~166,666 Mentioned India 56 days ago hyptechie.co.in 550 Views

Hyptechie is seeking an experienced Kubernetes Platform Technical Lead to lead and drive cloud-native infrastructure initiatives. The successful candidate will be instrumental in architecting and managing scalable platforms, ensuring that our infrastructure supports high-performance microservices and cloud-native applications. This role requires a visionary leader who can bridge the gap between development and operations to foster a robust DevOps

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AI ENGINEER (GENAI) @ P99SOFT

0 Negotiable or Not Mentioned India, Hyderabad 54 days ago p99soft.com 541 Views

We are looking for a passionate AI Engineer with hands-on experience in Generative AI to join our growing team in Hyderabad. The successful candidate will design and develop end-to-end generative AI solutions on AWS, focusing on Large Language Models (LLMs), Retrieval-Augmented Generation (RAG) pipelines, and prompt engineering. You will work with cutting-edge agentic workflows and modern frameworks to build real-world AI applications. This hybri

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