PHYSICAL DESIGN ENGINEER @ SKALEN SEMI
Skalen Semi is actively seeking highly skilled and experienced Physical Design Engineers to join their growing team. This role supports various clients, ranging from large established IT and design services to fast-growing mid-sized and start-up design companies. Successful candidates will be responsible for executing the complete physical design flow from RTL to GDS, ensuring high performance, low power, and robust design quality across various technology nodes, including cutting-edge 5nm, 3nm, and 7nm processes.
Key responsibilities involve complex tasks such as hierarchical floorplanning, partition management, advanced placement and routing, and meticulous clock tree synthesis (CTS). The engineer must also perform rigorous signoff checks, including static timing analysis (STA), IR drop analysis, Design Rule Checks (DRC), and Layout Versus Schematic (LVS) verification to guarantee a successful tapeout. The required experience level for this opportunity ranges from 5 to 15 years, reflecting the depth of expertise needed. The work locations available for this role are Bangalore, Hyderabad, and Noida.
Key responsibilities involve complex tasks such as hierarchical floorplanning, partition management, advanced placement and routing, and meticulous clock tree synthesis (CTS). The engineer must also perform rigorous signoff checks, including static timing analysis (STA), IR drop analysis, Design Rule Checks (DRC), and Layout Versus Schematic (LVS) verification to guarantee a successful tapeout. The required experience level for this opportunity ranges from 5 to 15 years, reflecting the depth of expertise needed. The work locations available for this role are Bangalore, Hyderabad, and Noida.
Key Requirements
Minimum 5 years of relevant experience in ASIC/SoC physical design and tapeout processes.
Proficiency in Physical Design flow from RTL to GDS.
Strong expertise in Floorplanning, Placement, and Routing techniques.
Hands-on experience with Clock Tree Synthesis (CTS) and handling complex timing constraints.
Strong knowledge of Static Timing Analysis (STA) and timing closure methodologies.
Experience working with advanced technology nodes (5nm, 3nm, 7nm).
Proficiency in using industry-standard EDA tools such as Synopsys ICC2/FusionCompiler and Cadence Innovus.
Ability to perform advanced signoff checks including DRC, LVS, and IR Drop Analysis.
Knowledge of partitioning, power planning, and overall design implementation strategies.
Familiarity with scripting languages (e.g., Python) for automation.