DESIGN VERIFICATION ENGINEER @ TIMES SEMICONDUCTORS
Times Semiconductors is hiring Design Verification Engineers to join our prominent engineering teams across India. You will be responsible for creating robust verification strategies for complex SoC and ASIC designs, utilizing UVM and SystemVerilog. This position offers the chance to work on high-impact projects that define the future of the global semiconductor industry.
Work locations include top Indian cities like Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. We welcome applications from engineers at all stages of their careers who are passionate about semiconductor innovation. This role requires a strong academic background in electronics and communication or electrical engineering and a dedication to high-quality design verification standards.
Work locations include top Indian cities like Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. We welcome applications from engineers at all stages of their careers who are passionate about semiconductor innovation. This role requires a strong academic background in electronics and communication or electrical engineering and a dedication to high-quality design verification standards.
Key Requirements
B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields.
Graduation date falling between 2012 and 2026.
Expertise in SystemVerilog and UVM (Universal Verification Methodology).
Experience developing testbenches and verification environments from scratch.
Proficiency in scripting with Python, Perl, or TCL.
Hands-on experience with simulation tools like VCS, Xcelium, or Questa.
In-depth knowledge of coverage-driven verification and assertion-based verification.
Strong debugging skills and ability to analyze complex RTL code.
Knowledge of computer architecture and digital logic design fundamentals.
Ability to work effectively within a cross-functional team environment.