DFT ENGINEERS @ SKALEN SEMI
Skalen Semi is looking for experienced DFT Engineers to join their dynamic team. This role is ideal for professionals with 5 to 15 years of experience in the semiconductor industry, working with large IT and design services as well as fast-growing mid-sized and start-up design services. The successful candidates will be responsible for various aspects of Design for Testability, ensuring high-quality silicon production and testing efficiency. The available positions are located across multiple hubs in India, including Bangalore, Hyderabad, and Noida. Candidates should be proficient in scan insertion, ATPG, MBIST, LBIST, and JTAG. Familiarity with industry-standard tools from Synopsys, Cadence, and Mentor/Siemens EDA is essential. This is a great opportunity to work on cutting-edge ASIC and SoC designs within a global career framework.
Key Requirements
Minimum 5 to 15 years of professional experience in DFT Engineering.
Extensive knowledge and hands-on experience with Scan Insertion techniques.
Proficiency in ATPG (Automatic Test Pattern Generation) processes.
Proven experience with MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test).
In-depth understanding of Boundary Scan and JTAG protocols.
Skilled in utilizing industry tools such as DFT Compiler and TestMAX.
Familiarity with Cadence Modus or Mentor Tessent tools.
Experience with verification and debugging using Synopsys SpyGlass and Verdi.
Hands-on experience with simulation tools like Cadence SimVision, Synopsys VCS, or Cadence Xcelium.
Strong background in ASIC and SoC design flows and digital electronics engineering.