ANALOG LAYOUT ENGINEER @ SKALEN SEMI
Skalen Semi is actively seeking highly experienced Analog Layout Engineers (AMS Layout Engineers) to join our team. We are partnering with large IT and design services firms, as well as fast-growing mid-sized and startup design services companies. This crucial role targets candidates with substantial expertise, requiring 5 to 15 years of relevant industry experience. Successful candidates will be responsible for performing complex analog/mixed-signal (AMS) layout designs for cutting-edge semiconductor products, ensuring optimal performance, density, and manufacturability.
This position offers opportunities to contribute significantly to advanced ASIC and SoC projects, covering technologies utilized in Microcontrollers, CPUs, GPUs, AI/ML chips, and IOT devices. The primary work locations for this role are within India's major technology hubs: Bangalore, Hyderabad, and Noida. Candidates must demonstrate deep knowledge of VLSI design principles, proficiency with industry-standard EDA tools (such as Synopsys, Cadence, and Siemens EDA), and familiarity with tapeout procedures and physical verification flows.
This position offers opportunities to contribute significantly to advanced ASIC and SoC projects, covering technologies utilized in Microcontrollers, CPUs, GPUs, AI/ML chips, and IOT devices. The primary work locations for this role are within India's major technology hubs: Bangalore, Hyderabad, and Noida. Candidates must demonstrate deep knowledge of VLSI design principles, proficiency with industry-standard EDA tools (such as Synopsys, Cadence, and Siemens EDA), and familiarity with tapeout procedures and physical verification flows.
Key Requirements
5 – 15 years of professional experience in Analog/AMS Layout design.
Proven expertise in utilizing industry-standard EDA tools (Cadence, Synopsys, Siemens EDA) for layout creation, extraction, and verification.
Strong understanding of deep sub-micron CMOS technologies and layout effects (e.g., matching, coupling, shielding, LVS/DRC closure).
Experience with physical verification flows and sign-off tools.
Ability to work closely with circuit design engineers to optimize layout for performance, power, and area.
Demonstrated experience in designing layouts for critical analog blocks (e.g., PLLs, ADCs, DACs, LDOs, SerDes).
Knowledge of semiconductor manufacturing processes and design for manufacturability (DFM).
Familiarity with scripting languages (e.g., Python, Perl) for automation of layout tasks.
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
Excellent communication and collaboration skills for working with globally distributed teams.