STA AND SYNTHESIS ENGINEERS @ SKALEN SEMI
Skalen Semi is actively seeking experienced STA and Synthesis Engineers to join their team. This role involves providing high-end design services to a range of clients, from large IT corporations to fast-growing mid-sized firms and innovative startups. Candidates will be responsible for critical aspects of the silicon development cycle, specifically focusing on Static Timing Analysis (STA), timing closure, and logic synthesis for complex ASIC and SoC projects. The ideal candidate will have extensive experience with RTL to GDSII flows and the ability to navigate through various design stages to ensure high-performance timing sign-off.
Key responsibilities include defining and optimizing timing constraints, performing multi-corner multi-mode (MCMM) analysis, and utilizing industry-leading EDA tools such as Synopsys PrimeTime and Cadence Tempus. The positions are available in several prominent technology hubs across India, including Bangalore, Hyderabad, and Noida, offering a dynamic environment for professional growth. Applicants should possess a deep understanding of digital electronics and silicon engineering to drive innovation in chip design for emerging technologies like AI, Machine Learning, and IoT. This is a significant opportunity to work on cutting-edge GPU, CPU, and microcontroller projects at various stages of the tapeout process.
Key responsibilities include defining and optimizing timing constraints, performing multi-corner multi-mode (MCMM) analysis, and utilizing industry-leading EDA tools such as Synopsys PrimeTime and Cadence Tempus. The positions are available in several prominent technology hubs across India, including Bangalore, Hyderabad, and Noida, offering a dynamic environment for professional growth. Applicants should possess a deep understanding of digital electronics and silicon engineering to drive innovation in chip design for emerging technologies like AI, Machine Learning, and IoT. This is a significant opportunity to work on cutting-edge GPU, CPU, and microcontroller projects at various stages of the tapeout process.
Key Requirements
Minimum of 5 to 15 years of professional experience in the semiconductor industry.
Proven expertise in Static Timing Analysis (STA) and achieving timing closure.
Proficiency in logic synthesis using industry-standard tools like Design Compiler or Cadence Genus.
Hands-on experience with the complete RTL to GDSII design flow.
Deep understanding of timing constraints and multi-corner multi-mode (MCMM) analysis.
Extensive experience with sign-off tools such as Synopsys PrimeTime or Cadence Tempus.
Familiarity with logical equivalence checking (LEC) using Formality or Conformal.
Strong background in digital design fundamentals and ASIC/SoC architectures.
Ability to debug and resolve complex timing issues in high-speed designs.
Knowledge of scripting languages like Python, Tcl, or Perl for EDA tool automation.