STA AND SYNTHESIS(LEC) ENGINEERS @ SKALEN SEMI
Skalen Semi is looking to recruit highly skilled STA and Synthesis(LEC) Engineers with a minimum of 6 to 12 years of experience. These positions are open for candidates who have previously worked with global design services powerhouses and are proficient in the semiconductor field. The primary work locations for these roles are Bangalore and Hyderabad, where engineers will tackle complex design challenges. Candidates will be expected to work within a fast-paced environment and deliver high-quality results for our global clients in the design services industry. Responsibilities include performing Static Timing Analysis, Synthesis, and Logic Equivalence Checks. Candidates should be well-versed in tools such as PrimeTime, Tempus, DesignCompiler, and Genus. Knowledge of timing closure, IR drop analysis, and RTL2Gates processes is crucial for success in this role. The opportunity involves working on advanced nodes and contributing to the development of cutting-edge SoC and ASIC designs. Successful hires will collaborate with multi-disciplinary teams to ensure hardware performance meets stringent design goals and timing requirements.
Key Requirements
Minimum 6 to 12 years of experience in VLSI or semiconductor design.
In-depth knowledge of Static Timing Analysis (STA) and timing closure.
Proficiency in Synthesis and Logic Equivalence Check (LEC) workflows.
Experience with industry-standard tools like PrimeTime or Tempus.
Hands-on experience with RTL2Gates, DesignCompiler, or Genus.
Understanding of MMMC (Multi-Mode Multi-Corner) analysis and SDF.
Knowledge of IR Drop and EM Analysis for integrated circuits.
Experience with advanced technology nodes (e.g., 7nm, 5nm).
Ability to perform Clock Tree Analysis (CTS) and Power Optimization.
Strong technical background in ASIC and SoC design methodologies.