PHYSICAL DESIGN ENGINEERS (3 POSITIONS) @ SKALENSEMI
SkalenSemi is seeking experienced Physical Design Engineers for three open positions to join our team in India. This role requires individuals with a strong background in the full physical design cycle, from floorplanning to sign-off. Candidates will be expected to work on-site at our facilities in either Bangalore or Pune, contributing to cutting-edge ASIC and chip design projects. The work model is strictly onsite, ensuring close collaboration with our technical teams in these key technology hubs.
The successful candidates will have between 6 to 12 years of relevant industry experience in the semiconductor field. Key responsibilities include handling complex physical design tasks such as Place and Route (PnR), Clock Tree Synthesis (CTS), and sign-off verification using industry-standard tools like Calibre. A robust understanding of VLSI design and the ability to ensure high-quality design outcomes are essential for this position. This is an excellent opportunity to grow within a dynamic technical environment focused on semiconductor innovation and high-performance chip design.
The successful candidates will have between 6 to 12 years of relevant industry experience in the semiconductor field. Key responsibilities include handling complex physical design tasks such as Place and Route (PnR), Clock Tree Synthesis (CTS), and sign-off verification using industry-standard tools like Calibre. A robust understanding of VLSI design and the ability to ensure high-quality design outcomes are essential for this position. This is an excellent opportunity to grow within a dynamic technical environment focused on semiconductor innovation and high-performance chip design.
Key Requirements
6-12 years of professional experience in Physical Design.
Strong hands-on experience in Physical Design flow and sign-off processes.
Proficiency in Place and Route (PnR) methodologies.
In-depth knowledge and experience with Clock Tree Synthesis (CTS).
Hands-on expertise with physical verification tools such as Calibre.
Strong background in ASIC Design and VLSI technologies.
Ability to work onsite at office locations in Bangalore or Pune.
Experience with Static Timing Analysis (STA) and timing closure.
Knowledge of sub-micron technology nodes (e.g., 7nm, 5nm).
Familiarity with industry-standard EDA tools for physical implementation.