0 Negotiable or Not Mentioned
India
13 days ago
skalensemi.com
883 Views
SkalenSemi is seeking experienced Physical Design Engineers for three open positions to join our team in India. This role requires individuals with a strong background in the full physical design cycle, from floorplanning to sign-off. Candidates will be expected to work on-site at our facilities in either Bangalore or Pune, contributing to cutting-edge ASIC and chip design projects. The work model is strictly onsite, ensuring close collaboration with our technical teams in these key technology hubs.
The successful candidates will have between 6 to 12 years of relevant industry experience in the semiconductor field. Key responsibilities include handling complex physical design tasks such as Place and Route (PnR), Clock Tree Synthesis (CTS), and sign-off verification using industry-standard tools like Calibre. A robust understanding of VLSI design and the ability to ensure high-quality design outcomes are essential for this position. This is an excellent opportunity to grow within a dynamic technical environment focused on semiconductor innovation and high-performance chip design.
Key Requirements
6-12 years of professional experience in Physical Design.
Strong hands-on experience in Physical Design flow and sign-off processes.
Proficiency in Place and Route (PnR) methodologies.
In-depth knowledge and experience with Clock Tree Synthesis (CTS).
Hands-on expertise with physical verification tools such as Calibre.
Strong background in ASIC Design and VLSI technologies.
Ability to work onsite at office locations in Bangalore or Pune.
Experience with Static Timing Analysis (STA) and timing closure.
Knowledge of sub-micron technology nodes (e.g., 7nm, 5nm).
Familiarity with industry-standard EDA tools for physical implementation.
0 Negotiable or Not Mentioned
India
14 days ago
skalensemi.com
677 Views
SkalenSemi is seeking experienced Physical Design Engineers to join our dynamic team in India. This role is crucial for our high-performance chip design projects, focusing on advanced technology nodes and complex integrated circuits. Candidates will be responsible for the complete physical design flow, ensuring high-quality netlist-to-GDSII implementation while meeting stringent power, performance, and area goals. The available work locations for these positions include Bangalore and Pune, operating under an onsite work model.
The ideal candidate will have between 6 and 12 years of relevant industry experience and a strong background in VLSI design. Key responsibilities include managing placement and routing (PnR), performing clock tree synthesis (CTS), and conducting final sign-off procedures using industry-standard verification tools like Calibre. We are looking for individuals with a proven track record in ASIC design and chip implementation who are ready to contribute to cutting-edge technology developments. There are currently 3 open positions available for this role.
Key Requirements
Minimum 6 to 12 years of professional experience in Physical Design.
Strong hands-on expertise in the entire Physical Design flow from netlist to GDSII.
Extensive experience with sign-off processes including timing, power, and physical verification.
Proficiency in Placement and Routing (PnR) techniques and industry-standard tools.
Demonstrated expertise in Clock Tree Synthesis (CTS) for high-frequency designs.
Practical experience using Calibre for DRC, LVS, and Antenna checks.
Solid understanding of ASIC Design methodologies and chip architecture.
Proven track record in Chip Design and implementation on advanced process nodes.
Ability to work effectively in an onsite environment in Bangalore or Pune.
Excellent technical problem-solving skills and the ability to work in a collaborative team environment.
0 Negotiable or Not Mentioned
India
28 days ago
skalensemi.com
1172 Views
Skalen Semi is seeking an experienced RTL Design Engineer to join a dynamic team working with global design services powerhouses. The role involves deep involvement in high-performance and low-power RTL development, microarchitecture definition, and SoC architecture design. You will be responsible for creating synthesis-ready RTL, managing timing closure (STA), and ensuring logical equivalence using tools such as Conformal or Formality.
This position is available in both Bangalore and Hyderabad. Candidates must have significant experience in the semiconductor industry, specifically within ASIC and chip design environments. Please note that this is a senior-level position requiring 6 to 12 years of relevant experience; applications from freshers or interns are not being accepted at this time.
Key Requirements
6 to 12 years of professional experience in RTL Design and Development.
Proven expertise in Microarchitecture and SoC Architecture design.
Proficiency in Hardware Description Languages (HDL) like SystemVerilog and Verilog.
Experience in IP Design and Subsystem Design for high-performance systems.
Solid understanding of Low Power RTL design and Clocking Architecture.
Familiarity with Pipeline Design and Bus/Interconnect architectures.
Demonstrated ability to deliver Synthesis-Ready RTL and achieve Timing Closure (STA).
Hands-on experience with LEC tools such as Conformal or Formality.
Knowledge of DFT-ready RTL design and implementation best practices.
Strong background in ASIC design flows and the semiconductor industry.
0 Negotiable or Not Mentioned
India
31 days ago
skalensemi.com
1084 Views
Skalen Semi is looking to recruit highly skilled STA and Synthesis(LEC) Engineers with a minimum of 6 to 12 years of experience. These positions are open for candidates who have previously worked with global design services powerhouses and are proficient in the semiconductor field. The primary work locations for these roles are Bangalore and Hyderabad, where engineers will tackle complex design challenges. Candidates will be expected to work within a fast-paced environment and deliver high-quality results for our global clients in the design services industry. Responsibilities include performing Static Timing Analysis, Synthesis, and Logic Equivalence Checks. Candidates should be well-versed in tools such as PrimeTime, Tempus, DesignCompiler, and Genus. Knowledge of timing closure, IR drop analysis, and RTL2Gates processes is crucial for success in this role. The opportunity involves working on advanced nodes and contributing to the development of cutting-edge SoC and ASIC designs. Successful hires will collaborate with multi-disciplinary teams to ensure hardware performance meets stringent design goals and timing requirements.
Key Requirements
Minimum 6 to 12 years of experience in VLSI or semiconductor design.
In-depth knowledge of Static Timing Analysis (STA) and timing closure.
Proficiency in Synthesis and Logic Equivalence Check (LEC) workflows.
Experience with industry-standard tools like PrimeTime or Tempus.
Hands-on experience with RTL2Gates, DesignCompiler, or Genus.
Understanding of MMMC (Multi-Mode Multi-Corner) analysis and SDF.
Knowledge of IR Drop and EM Analysis for integrated circuits.
Experience with advanced technology nodes (e.g., 7nm, 5nm).
Ability to perform Clock Tree Analysis (CTS) and Power Optimization.
Strong technical background in ASIC and SoC design methodologies.
0 Negotiable or Not Mentioned
India, Hyderabad
10 days ago
karashatech.com
688 Views
KarashaTech is seeking highly skilled and experienced Design Verification (DV) Engineers to join our rapidly growing technical team in Hyderabad. In this role, you will be responsible for the verification of complex integrated circuits, ensuring that designs meet functional requirements and power specifications. You will work closely with design teams to define verification strategies and develop robust testbenches that leverage advanced industry methodologies. This is an excellent opportunity for a professional looking to work on cutting-edge semiconductor projects within a collaborative and innovative environment.The successful candidate will demonstrate a deep understanding of the full verification lifecycle, from planning to coverage closure. You will be expected to handle power-aware simulations and debug intricate issues across RTL and UPF models. With a requirement for at least five years of experience, we are looking for engineers who can hit the ground running and contribute to our high-standards of silicon quality. Candidates with a short notice period are highly preferred to meet our current project timelines.
Key Requirements
Minimum of 5 years of professional experience in Design Verification.
Strong hands-on experience with SystemVerilog for verification.
Advanced proficiency in Universal Verification Methodology (UVM).
Solid understanding of Unified Power Format (UPF) and Power Intent Modeling.
Proven experience conducting Power-Aware Simulations.
In-depth knowledge of Power Domains and Power States.
Familiarity with Isolation, Retention, and Level Shifters within designs.
Understanding of the interactions between Reset and Power states.
Strong debugging skills across RTL, UPF, and various Testbench environments.
Ability to join within a short notice period of approximately 15 days.
0 Negotiable or Not Mentioned
India
17 days ago
gsvrtalent.com
1032 Views
GSVR Talent Solutions Pvt Ltd is hiring experienced DDR Verification Engineers to join their high-performance semiconductor team. This role involves working on cutting-edge technology including next-generation AI chips and high-speed memory interfaces. The chosen candidate will be responsible for the verification of DDR3, DDR4, DDR5, and LPDDR4/LPDDR5 controllers, ensuring that every memory transaction behaves exactly as expected before silicon production. You will develop UVM-based verification environments using DDR VIPs and work closely with senior VLSI engineering teams.
In this position, you will create and debug complex memory traffic scenarios and ensure strict protocol compliance through functional coverage closure. The role requires a strong debugging and analytical mindset to solve intricate hardware validation challenges. By joining this project, you will contribute to the development of high-performance computing systems and collaborate with experts in the VLSI industry to deliver reliable hardware solutions for modern technology infrastructures.
Key Requirements
At least 4 years of professional experience in Design Verification within the VLSI or semiconductor industry.
Strong technical knowledge of DDR protocols including DDR3, DDR4, and DDR5.
Hands-on expertise with LPDDR4 and LPDDR5 memory architectures and controllers.
Proven experience in developing and maintaining UVM-based (Universal Verification Methodology) environments.
Advanced proficiency in using SystemVerilog for hardware verification tasks.
Direct experience working with DDR Verification IPs (VIPs) and associated debugging tools.
Ability to create, simulate, and debug complex memory traffic scenarios for validation.
Demonstrated ability to ensure protocol compliance and achieve functional coverage closure.
A strong debugging and analytical mindset to resolve architectural and functional issues.
Ability to collaborate effectively with cross-functional engineering teams on high-performance computing projects.
0 Negotiable or Not Mentioned
India
20 days ago
techedge-solution.com
571 Views
TechEdge Solution is seeking experienced professionals for the role of Senior Designer (STA). This position is ideal for candidates with over 7 years of expertise in VLSI and Physical Design, specifically focusing on timing analysis and design methodologies. The role involves working on high-stakes projects where you will ensure high-quality, consistent, and user-friendly design outputs. We are specifically looking for immediate joiners or those with a notice period of up to 30 days to join our dynamic engineering team.
Key responsibilities include collaborating with various stakeholders to understand complex design requirements, developing prototypes, and validating design concepts. You will work closely with cross-functional teams including Development, QA, and Product to ensure project success. Additionally, as a Senior Designer, you will be expected to mentor junior team members and provide technical leadership. Possible work locations for this role within India include Bangalore, Hyderabad, Chennai, and Noida. Preferred skills include familiarity with UX principles and design tools like Figma or Adobe XD to enhance cross-disciplinary collaboration.
Key Requirements
Strong experience in Static Timing Analysis (STA)
Expertise in Constraint Development and TCL Scripting
Good understanding of Synthesis (Syn) and APR (Place and Route)
Proven experience in Timing Closure and Physical Design
At least 7 years of relevant industry experience for Bangalore, Hyderabad, Chennai, or Noida locations
Minimum of 15 years of experience specifically for senior-level placement in Bangalore
Ability to collaborate with stakeholders to understand design requirements
Experience developing prototypes and validating design concepts
Capability to work closely with cross-functional teams including Dev, QA, and Product
Strong mentorship skills for guiding junior team members
0 Negotiable or Not Mentioned
India
11 days ago
GMAIL.COM
894 Views
Times Semiconductors is seeking talented RTL Design Engineers to join our expanding team in India. In this role, you will play a pivotal part in designing and developing advanced semiconductor systems, focusing on ASIC and SoC innovation. You will work alongside industry experts to push the boundaries of what is possible in VLSI design and microelectronics.
Candidates can be based in several key tech hubs in India, including Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. Whether you are a fresh graduate or an experienced professional, we offer a dynamic platform for career advancement and technical skill development. Eligibility includes B.E/B.Tech or M.E/M.Tech graduates from the batches of 2012 through 2026.
Key Requirements
Bachelor's or Master's degree in ECE, EEE, or related engineering fields.
Graduation year between 2012 and 2026.
Strong proficiency in Verilog or SystemVerilog for hardware description.
Knowledge of SoC integration processes and methodologies.
Experience with scripting languages such as Python, TCL, or Perl.
Familiarity with industry-standard EDA tools like VCS, Xcelium, or Questa.
Solid understanding of digital logic design and computer architecture.
Ability to work in a fast-paced environment on complex ASIC projects.
Excellent analytical and problem-solving skills for debugging design issues.
Strong communication skills for collaborating with global engineering teams.
0 Negotiable or Not Mentioned
India
11 days ago
GMAIL.COM
607 Views
Times Semiconductors is hiring Design Verification Engineers to join our prominent engineering teams across India. You will be responsible for creating robust verification strategies for complex SoC and ASIC designs, utilizing UVM and SystemVerilog. This position offers the chance to work on high-impact projects that define the future of the global semiconductor industry.
Work locations include top Indian cities like Bengaluru, Hyderabad, Chennai, Noida, Visakhapatnam, and Kochi. We welcome applications from engineers at all stages of their careers who are passionate about semiconductor innovation. This role requires a strong academic background in electronics and communication or electrical engineering and a dedication to high-quality design verification standards.
Key Requirements
B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields.
Graduation date falling between 2012 and 2026.
Expertise in SystemVerilog and UVM (Universal Verification Methodology).
Experience developing testbenches and verification environments from scratch.
Proficiency in scripting with Python, Perl, or TCL.
Hands-on experience with simulation tools like VCS, Xcelium, or Questa.
In-depth knowledge of coverage-driven verification and assertion-based verification.
Strong debugging skills and ability to analyze complex RTL code.
Knowledge of computer architecture and digital logic design fundamentals.
Ability to work effectively within a cross-functional team environment.
0 Negotiable or Not Mentioned
India
12 days ago
apar.com
696 Views
APAR Cable Solutions is actively seeking a professional Manager-Sales to join our team and spearhead business growth in major Indian hubs including Bangalore, Vizag, and Vijayawada. This role is central to driving MEP project wins by leveraging deep technical expertise and strong industry connections. You will be responsible for overseeing project sales within the building segment, specifically focusing on our high-quality electrical product lines. Possible work locations for this vacancy include Bangalore, Vizag, and Vijayawada. The successful candidate will be expected to work closely with MEP consultants, employing a Total Cost of Ownership (TCO) methodology to deliver value-driven solutions. Your duties will also involve the strategic management of project distributors and dealers to ensure seamless service delivery. With a focus on market research and competitive intelligence, you will play a key role in identifying new opportunities and maintaining APAR Cable Solutions position as a market leader in the region.
Key Requirements
Must possess a BE or Diploma in Engineering.
Minimum of 10 years of professional experience in sales management.
Proven background in project sales within the building segment for electrical products.
Demonstrated experience collaborating with MEP consultants and stakeholders.
Strong understanding and application of the Total Cost of Ownership (TCO) approach.
Experience in managing project distributors and dealers for electrical product lines.
High proficiency in conducting market research and trend analysis.
Expertise in competitive analysis and gathering strategic market intelligence.
Exceptional interpersonal and communication skills to influence decision-makers.
Ability to drive sales growth and meet targets in a fast-paced environment.