PHYSICAL DESIGN ENGINEERS (3 POSITIONS) @ SKALENSEMI
SkalenSemi is seeking experienced Physical Design Engineers to join our dynamic team in India. This role is crucial for our high-performance chip design projects, focusing on advanced technology nodes and complex integrated circuits. Candidates will be responsible for the complete physical design flow, ensuring high-quality netlist-to-GDSII implementation while meeting stringent power, performance, and area goals. The available work locations for these positions include Bangalore and Pune, operating under an onsite work model.
The ideal candidate will have between 6 and 12 years of relevant industry experience and a strong background in VLSI design. Key responsibilities include managing placement and routing (PnR), performing clock tree synthesis (CTS), and conducting final sign-off procedures using industry-standard verification tools like Calibre. We are looking for individuals with a proven track record in ASIC design and chip implementation who are ready to contribute to cutting-edge technology developments. There are currently 3 open positions available for this role.
The ideal candidate will have between 6 and 12 years of relevant industry experience and a strong background in VLSI design. Key responsibilities include managing placement and routing (PnR), performing clock tree synthesis (CTS), and conducting final sign-off procedures using industry-standard verification tools like Calibre. We are looking for individuals with a proven track record in ASIC design and chip implementation who are ready to contribute to cutting-edge technology developments. There are currently 3 open positions available for this role.
Key Requirements
Minimum 6 to 12 years of professional experience in Physical Design.
Strong hands-on expertise in the entire Physical Design flow from netlist to GDSII.
Extensive experience with sign-off processes including timing, power, and physical verification.
Proficiency in Placement and Routing (PnR) techniques and industry-standard tools.
Demonstrated expertise in Clock Tree Synthesis (CTS) for high-frequency designs.
Practical experience using Calibre for DRC, LVS, and Antenna checks.
Solid understanding of ASIC Design methodologies and chip architecture.
Proven track record in Chip Design and implementation on advanced process nodes.
Ability to work effectively in an onsite environment in Bangalore or Pune.
Excellent technical problem-solving skills and the ability to work in a collaborative team environment.