RTL DESIGN ENGINEER @ SKALEN SEMI
Skalen Semi is seeking an experienced RTL Design Engineer to join a dynamic team working with global design services powerhouses. The role involves deep involvement in high-performance and low-power RTL development, microarchitecture definition, and SoC architecture design. You will be responsible for creating synthesis-ready RTL, managing timing closure (STA), and ensuring logical equivalence using tools such as Conformal or Formality.
This position is available in both Bangalore and Hyderabad. Candidates must have significant experience in the semiconductor industry, specifically within ASIC and chip design environments. Please note that this is a senior-level position requiring 6 to 12 years of relevant experience; applications from freshers or interns are not being accepted at this time.
This position is available in both Bangalore and Hyderabad. Candidates must have significant experience in the semiconductor industry, specifically within ASIC and chip design environments. Please note that this is a senior-level position requiring 6 to 12 years of relevant experience; applications from freshers or interns are not being accepted at this time.
Key Requirements
6 to 12 years of professional experience in RTL Design and Development.
Proven expertise in Microarchitecture and SoC Architecture design.
Proficiency in Hardware Description Languages (HDL) like SystemVerilog and Verilog.
Experience in IP Design and Subsystem Design for high-performance systems.
Solid understanding of Low Power RTL design and Clocking Architecture.
Familiarity with Pipeline Design and Bus/Interconnect architectures.
Demonstrated ability to deliver Synthesis-Ready RTL and achieve Timing Closure (STA).
Hands-on experience with LEC tools such as Conformal or Formality.
Knowledge of DFT-ready RTL design and implementation best practices.
Strong background in ASIC design flows and the semiconductor industry.