DV-GLS ENGINEER @ GSVR TALENT SOLUTIONS PVT LTD
GSVR Talent Solutions is actively seeking a highly skilled Design Verification Engineer specializing in Gate-Level Simulation (GLS). This role is centered within the rapidly evolving semiconductor industry, requiring candidates who possess a minimum of four years of relevant experience in VLSI verification. The successful applicant will be crucial in ensuring the robustness and accuracy of complex digital designs through rigorous testing and simulation processes. This opportunity is ideal for professionals passionate about advanced verification flows and detail-oriented technical execution.The core responsibilities include utilizing SystemVerilog and UVM environments to execute functional verification tasks. A major focus of this position involves Gate-Level Simulation (GLS), requiring expertise in handling SDF annotation, performing detailed timing checks, and debugging complex simulation failures. The engineer will also manage regression runs and perform comprehensive coverage analysis to meet stringent design verification goals within the VLSI domain.
Key Requirements
SystemVerilog & UVM expertise
Proficiency in Gate-Level Simulation (GLS)
Experience with SDF Annotation
Ability to perform Timing Checks and Debugging
Strong background in Functional Verification
Skill in Regression and Coverage Analysis
Minimum 4 years of experience in VLSI verification domain
Expertise in advanced verification methodologies and flows
Strong analytical and problem-solving skills related to silicon debug
Deep understanding of semiconductor industry practices