RTL DESIGN ENGINEER @ SKALEN SEMI
Skalen Semi is seeking highly experienced and skilled RTL Design Engineers to join our dynamic team. This critical role involves working on cutting-edge projects for a diverse clientele, including large IT firms, design services companies, and fast-growing mid-sized startups. Candidates must possess significant experience, ranging from 5 to 15 years, in the field of RTL design and microarchitecture development. The primary responsibilities will encompass all stages of the digital design flow, from specification definition to tapeout preparation, ensuring high-quality and robust silicon implementation.
The ideal candidate will demonstrate mastery of SystemVerilog and other HDLs, coupled with deep knowledge of ASIC and SoC design methodologies. Key activities include advanced RTL coding, performing thorough RTL quality checks, and supporting gate-level simulations. The role requires collaboration across teams to deliver complex IC solutions for applications such as Microcontrollers, CPU/GPU, AI, and IoT devices. The position is based in India, with potential work locations in Bangalore, Hyderabad, and Noida, depending on project needs and candidate preference. We utilize industry-leading EDA tools from vendors like Synopsys, Cadence, and SiemensEDA to drive innovation in the semiconductor space.
The ideal candidate will demonstrate mastery of SystemVerilog and other HDLs, coupled with deep knowledge of ASIC and SoC design methodologies. Key activities include advanced RTL coding, performing thorough RTL quality checks, and supporting gate-level simulations. The role requires collaboration across teams to deliver complex IC solutions for applications such as Microcontrollers, CPU/GPU, AI, and IoT devices. The position is based in India, with potential work locations in Bangalore, Hyderabad, and Noida, depending on project needs and candidate preference. We utilize industry-leading EDA tools from vendors like Synopsys, Cadence, and SiemensEDA to drive innovation in the semiconductor space.
Key Requirements
5 – 15 years of professional experience in RTL Design and verification.
Expertise in RTL Coding and Microarchitecture development.
Proficiency in Hardware Description Languages (HDL), specifically SystemVerilog.
Experience with RTL Quality Check processes and methodologies.
Familiarity with Gate Level Simulation and debugging techniques.
Experience working on complex Semiconductor, ASIC, or SoC projects.
Strong knowledge of Digital Design principles and VLSI concepts.
Familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence, SiemensEDA).
Understanding of CPU/GPU architectures and Tapeout processes.
Ability to utilize C/C++ and scripting languages like Python for design and verification tasks.