DDR VERIFICATION ENGINEER @ GSVR TALENT SOLUTIONS PVT LTD
GSVR Talent Solutions Pvt Ltd is hiring experienced DDR Verification Engineers to join their high-performance semiconductor team. This role involves working on cutting-edge technology including next-generation AI chips and high-speed memory interfaces. The chosen candidate will be responsible for the verification of DDR3, DDR4, DDR5, and LPDDR4/LPDDR5 controllers, ensuring that every memory transaction behaves exactly as expected before silicon production. You will develop UVM-based verification environments using DDR VIPs and work closely with senior VLSI engineering teams.
In this position, you will create and debug complex memory traffic scenarios and ensure strict protocol compliance through functional coverage closure. The role requires a strong debugging and analytical mindset to solve intricate hardware validation challenges. By joining this project, you will contribute to the development of high-performance computing systems and collaborate with experts in the VLSI industry to deliver reliable hardware solutions for modern technology infrastructures.
In this position, you will create and debug complex memory traffic scenarios and ensure strict protocol compliance through functional coverage closure. The role requires a strong debugging and analytical mindset to solve intricate hardware validation challenges. By joining this project, you will contribute to the development of high-performance computing systems and collaborate with experts in the VLSI industry to deliver reliable hardware solutions for modern technology infrastructures.
Key Requirements
At least 4 years of professional experience in Design Verification within the VLSI or semiconductor industry.
Strong technical knowledge of DDR protocols including DDR3, DDR4, and DDR5.
Hands-on expertise with LPDDR4 and LPDDR5 memory architectures and controllers.
Proven experience in developing and maintaining UVM-based (Universal Verification Methodology) environments.
Advanced proficiency in using SystemVerilog for hardware verification tasks.
Direct experience working with DDR Verification IPs (VIPs) and associated debugging tools.
Ability to create, simulate, and debug complex memory traffic scenarios for validation.
Demonstrated ability to ensure protocol compliance and achieve functional coverage closure.
A strong debugging and analytical mindset to resolve architectural and functional issues.
Ability to collaborate effectively with cross-functional engineering teams on high-performance computing projects.