0 Negotiable or Not Mentioned
USA
71 days ago
GMAIL.COM
15 Applied 11 Pro Applied
Become a Design Verification Engineer at Times Semiconductors and ensure the reliability of the next generation of semiconductor products. Your primary responsibility will be to develop and execute comprehensive verification plans using advanced methodologies to ensure design specifications are met perfectly. You will be an essential part of the design cycle, working to identify and resolve complex design bugs before production.
This role is open at our various USA locations, including California, Chicago, Boston, and New York. We are recruiting at all levels, from Engineers (0-4 years) to Leads (5-10 years) and Managers (12-15 years). Join us to work on cutting-edge technologies in a environment that values technical excellence and innovation in the VLSI domain.
Key Requirements
B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields.
Graduation date falling between 2012 and 2026.
Expertise in SystemVerilog and UVM (Universal Verification Methodology).
Experience developing testbenches and verification environments from scratch.
Proficiency in scripting with Python, Perl, or TCL.
0 Negotiable or Not Mentioned
USA
85 days ago
skalensemi.com
13 Applied 1 Casual Applied
SkalenSemi is currently seeking highly experienced professionals for the position of Lead Design Verification to support a large-sized IT and global design services Hyperscaler. This recruitment drive is for approximately 25 to 30 open positions, highlighting a significant expansion in their design verification capabilities. Work locations for these roles include Santa Clara, CA, and Texas, TX, offering opportunities for senior experts to work in major tech hubs. The role involves working at the forefront of semiconductor technology within a global design environment.
The successful candidates will lead complex verification projects, utilizing advanced methodologies to ensure the integrity of high-performance chips. Key responsibilities include defining verification architectures, developing comprehensive testbenches, and executing functional verification strategies for IP and SoC designs. Given the seniority of the role, candidates are expected to mentor junior engineers and drive technical excellence across the verification lifecycle. There is no salary mentioned in the original job post for this position.
Key Requirements
Minimum of 8 to 20 years of professional experience in Lead Design Verification.
Extensive expertise in SystemVerilog and Universal Verification Methodology (UVM).
Proven track record in Functional Verification, RTL Verification, and SoC Verification.
Deep knowledge of IP Verification and Subsystem Verification techniques.
Experience in developing robust Verification Architectures and Testbenches.
0 Negotiable or Not Mentioned
USA
79 days ago
skalensemi.com
9 Applied 6 Pro Applied
SkalenSemi is currently seeking highly experienced Design Verification Engineers to join our growing team in the United States. We have 20 open positions available for professionals with 6 to 15 years of expertise in the semiconductor industry. Successful candidates will be working on-site at one of our key locations, which include Austin, Texas; Santa Clara, California; and Boston, Massachusetts. This is a significant opportunity to contribute to high-impact projects involving Data Fabric and complex chip architectures within a leading-edge environment.
The role focuses on developing robust verification environments and executing comprehensive test plans to ensure the integrity of advanced ASIC designs. Candidates will utilize SystemVerilog and UVM methodologies to perform rigorous testing and debugging of RTL code. Please be advised that these roles are strictly for experienced professionals and are not suitable for entry-level candidates or freshers. You will be expected to collaborate with cross-functional teams to drive verification excellence and meet project milestones in a fast-paced technical setting.
Key Requirements
Minimum 6 to 15 years of professional experience in Design Verification.
Deep expertise in SystemVerilog for testbench development.
Proven experience with UVM (Universal Verification Methodology) frameworks.
Strong knowledge of Formal Verification techniques and tools.
Extensive background in ASIC and RTL design verification processes.
0 Negotiable or Not Mentioned
USA
71 days ago
GMAIL.COM
12 Applied 4 Ultra Applied
Join Times Semiconductors as an RTL Design Engineer to help power the future of VLSI technology. This role involves working on cutting-edge SoC, ASIC, and Analog technologies within a collaborative and innovative environment. You will be responsible for developing high-performance RTL code and ensuring design integrity throughout the development lifecycle for various semiconductor projects.
This position is available at multiple locations across the USA, including California, Chicago, Boston, and New York. We are looking for passionate individuals ranging from entry-level engineers with 0-4 years of experience to seasoned managers with 12-15 years of expertise in the field. This is an excellent opportunity to grow your career in the semiconductor industry with a forward-thinking company.
Key Requirements
Bachelor's or Master's degree in ECE, EEE, or related engineering fields.
Graduation year between 2012 and 2026.
Strong proficiency in Verilog or SystemVerilog for hardware description.
Knowledge of SoC integration processes and methodologies.
Experience with scripting languages such as Python, TCL, or Perl.
0 Negotiable or Not Mentioned
USA
73 days ago
skalensemi.com
9 Applied 3 Ultra Applied
SkalenSemi is currently seeking highly experienced Design Verification Engineers for 20 open positions across the United States. These roles are critical to our semiconductor operations and require professionals with a robust background in the industry, specifically with 6 to 15 years of dedicated experience. The work model is strictly onsite, with potential placements in Austin, Texas; Santa Clara, California; or Boston, Massachusetts. We are looking for candidates who can hit the ground running and contribute to our high-level chip design projects immediately. Please note that these roles are tailored for senior professionals and are not suitable for freshers or entry-level applicants.
In this role, engineers will be responsible for complex verification tasks using advanced methodologies. This includes working with SystemVerilog and UVM to ensure the functional integrity of data fabrics and other sophisticated RTL designs. The job involves applying formal verification techniques and collaborating closely with design teams to meet rigorous quality standards in ASIC development. Successful applicants will join a dynamic technical environment at SkalenSemi, contributing to the development of next-generation semiconductor technologies. Applicants should submit their updated resumes to the provided contact email for consideration.
Key Requirements
6 to 15 years of professional experience in Design Verification.
Advanced proficiency in SystemVerilog for hardware description and verification.
Extensive experience with Universal Verification Methodology (UVM).
Proven track record with Formal Verification techniques and tools.
Strong understanding of RTL design and the ASIC development lifecycle.
0 Negotiable or Not Mentioned
USA
71 days ago
GMAIL.COM
15 Applied 11 Pro Applied
Join Times Semiconductors as a DFT Engineer and contribute to the reliability and testability of our advanced VLSI designs. You will be involved in implementing Design-for-Test strategies, including Scan, ATPG, and MBIST, ensuring our semiconductor products are manufactured with the highest quality and yield. This role is crucial for bridging the gap between design and high-volume manufacturing.
This opportunity is available at our offices in the USA, specifically in California, Chicago, Boston, and New York. We provide a collaborative platform for engineers to apply their expertise in DFT tools and methodologies to solve complex silicon testing challenges. Whether you are an early-career engineer or a seasoned professional, we invite you to be part of our innovation journey.
Key Requirements
Bachelor's or Master's degree in ECE, EEE, or a similar field.
Graduation year range: 2012 to 2026.
Strong understanding of DFT fundamentals including Scan and ATPG.
Knowledge of MBIST (Memory Built-In Self-Test) and LBIST (Logic BIST).
Experience with DFT tools like Tessent, Modus, or Genus.