LEAD DESIGN VERIFICATION (25 TO 30 POSITIONS) @ SKALENSEMI
SkalenSemi is currently seeking highly experienced professionals for the position of Lead Design Verification to support a large-sized IT and global design services Hyperscaler. This recruitment drive is for approximately 25 to 30 open positions, highlighting a significant expansion in their design verification capabilities. Work locations for these roles include Santa Clara, CA, and Texas, TX, offering opportunities for senior experts to work in major tech hubs. The role involves working at the forefront of semiconductor technology within a global design environment.
The successful candidates will lead complex verification projects, utilizing advanced methodologies to ensure the integrity of high-performance chips. Key responsibilities include defining verification architectures, developing comprehensive testbenches, and executing functional verification strategies for IP and SoC designs. Given the seniority of the role, candidates are expected to mentor junior engineers and drive technical excellence across the verification lifecycle. There is no salary mentioned in the original job post for this position.
The successful candidates will lead complex verification projects, utilizing advanced methodologies to ensure the integrity of high-performance chips. Key responsibilities include defining verification architectures, developing comprehensive testbenches, and executing functional verification strategies for IP and SoC designs. Given the seniority of the role, candidates are expected to mentor junior engineers and drive technical excellence across the verification lifecycle. There is no salary mentioned in the original job post for this position.
Key Requirements
Minimum of 8 to 20 years of professional experience in Lead Design Verification.
Extensive expertise in SystemVerilog and Universal Verification Methodology (UVM).
Proven track record in Functional Verification, RTL Verification, and SoC Verification.
Deep knowledge of IP Verification and Subsystem Verification techniques.
Experience in developing robust Verification Architectures and Testbenches.
Proficiency in Coverage-Driven Verification and Constrained Random Verification.
Advanced skills in Assertion-Based Verification (SVA) and Scoreboarding.
Demonstrated ability in Debugging and Waveform Debug using industry-standard tools.
Familiarity with Simulation and Emulation-Ready RTL processes.
Experience in Pre-Silicon Validation within a high-performance computing environment.