DESIGN VERIFICATION ENGINEERS (20 POSITIONS) @ SKALENSEMI
SkalenSemi is currently seeking highly experienced Design Verification Engineers for 20 open positions across the United States. These roles are critical to our semiconductor operations and require professionals with a robust background in the industry, specifically with 6 to 15 years of dedicated experience. The work model is strictly onsite, with potential placements in Austin, Texas; Santa Clara, California; or Boston, Massachusetts. We are looking for candidates who can hit the ground running and contribute to our high-level chip design projects immediately. Please note that these roles are tailored for senior professionals and are not suitable for freshers or entry-level applicants.
In this role, engineers will be responsible for complex verification tasks using advanced methodologies. This includes working with SystemVerilog and UVM to ensure the functional integrity of data fabrics and other sophisticated RTL designs. The job involves applying formal verification techniques and collaborating closely with design teams to meet rigorous quality standards in ASIC development. Successful applicants will join a dynamic technical environment at SkalenSemi, contributing to the development of next-generation semiconductor technologies. Applicants should submit their updated resumes to the provided contact email for consideration.
In this role, engineers will be responsible for complex verification tasks using advanced methodologies. This includes working with SystemVerilog and UVM to ensure the functional integrity of data fabrics and other sophisticated RTL designs. The job involves applying formal verification techniques and collaborating closely with design teams to meet rigorous quality standards in ASIC development. Successful applicants will join a dynamic technical environment at SkalenSemi, contributing to the development of next-generation semiconductor technologies. Applicants should submit their updated resumes to the provided contact email for consideration.
Key Requirements
6 to 15 years of professional experience in Design Verification.
Advanced proficiency in SystemVerilog for hardware description and verification.
Extensive experience with Universal Verification Methodology (UVM).
Proven track record with Formal Verification techniques and tools.
Strong understanding of RTL design and the ASIC development lifecycle.
Knowledge of Data Fabric architectures and chip design principles.
Ability to work onsite at Austin, TX, Santa Clara, CA, or Boston, MA.
Experience in developing and maintaining complex testbenches.
Strong debugging skills at the register-transfer level.
Excellent analytical and problem-solving abilities within semiconductor environments.