DFT ENGINEER @ TIMES SEMICONDUCTORS
Join Times Semiconductors as a DFT Engineer and contribute to the reliability and testability of our advanced VLSI designs. You will be involved in implementing Design-for-Test strategies, including Scan, ATPG, and MBIST, ensuring our semiconductor products are manufactured with the highest quality and yield. This role is crucial for bridging the gap between design and high-volume manufacturing.
This opportunity is available at our offices in the USA, specifically in California, Chicago, Boston, and New York. We provide a collaborative platform for engineers to apply their expertise in DFT tools and methodologies to solve complex silicon testing challenges. Whether you are an early-career engineer or a seasoned professional, we invite you to be part of our innovation journey.
This opportunity is available at our offices in the USA, specifically in California, Chicago, Boston, and New York. We provide a collaborative platform for engineers to apply their expertise in DFT tools and methodologies to solve complex silicon testing challenges. Whether you are an early-career engineer or a seasoned professional, we invite you to be part of our innovation journey.
Key Requirements
Bachelor's or Master's degree in ECE, EEE, or a similar field.
Graduation year range: 2012 to 2026.
Strong understanding of DFT fundamentals including Scan and ATPG.
Knowledge of MBIST (Memory Built-In Self-Test) and LBIST (Logic BIST).
Experience with DFT tools like Tessent, Modus, or Genus.
Proficiency in scripting using Python, TCL, or Perl for automation.
Understanding of the physical design flow and its impact on DFT.
Familiarity with JTAG and boundary scan standards.
Strong problem-solving skills for silicon failure analysis and debug.
Ability to communicate technical findings effectively with design and manufacturing teams.