DESIGN VERIFICATION ENGINEERS (20 POSITIONS) @ SKALENSEMI
SkalenSemi is currently seeking highly experienced Design Verification Engineers to join our growing team in the United States. We have 20 open positions available for professionals with 6 to 15 years of expertise in the semiconductor industry. Successful candidates will be working on-site at one of our key locations, which include Austin, Texas; Santa Clara, California; and Boston, Massachusetts. This is a significant opportunity to contribute to high-impact projects involving Data Fabric and complex chip architectures within a leading-edge environment.
The role focuses on developing robust verification environments and executing comprehensive test plans to ensure the integrity of advanced ASIC designs. Candidates will utilize SystemVerilog and UVM methodologies to perform rigorous testing and debugging of RTL code. Please be advised that these roles are strictly for experienced professionals and are not suitable for entry-level candidates or freshers. You will be expected to collaborate with cross-functional teams to drive verification excellence and meet project milestones in a fast-paced technical setting.
The role focuses on developing robust verification environments and executing comprehensive test plans to ensure the integrity of advanced ASIC designs. Candidates will utilize SystemVerilog and UVM methodologies to perform rigorous testing and debugging of RTL code. Please be advised that these roles are strictly for experienced professionals and are not suitable for entry-level candidates or freshers. You will be expected to collaborate with cross-functional teams to drive verification excellence and meet project milestones in a fast-paced technical setting.
Key Requirements
Minimum 6 to 15 years of professional experience in Design Verification.
Deep expertise in SystemVerilog for testbench development.
Proven experience with UVM (Universal Verification Methodology) frameworks.
Strong knowledge of Formal Verification techniques and tools.
Extensive background in ASIC and RTL design verification processes.
Experience working with Data Fabric or high-speed interconnects.
Ability to develop comprehensive verification plans from architecture specifications.
Proficiency in debugging complex hardware designs using industry-standard simulators.
Familiarity with scripting languages such as Python or Perl for automation.
Excellent analytical and problem-solving skills in a VLSI environment.