DESIGN VERIFICATION ENGINEER @ TIMES SEMICONDUCTORS
Become a Design Verification Engineer at Times Semiconductors and ensure the reliability of the next generation of semiconductor products. Your primary responsibility will be to develop and execute comprehensive verification plans using advanced methodologies to ensure design specifications are met perfectly. You will be an essential part of the design cycle, working to identify and resolve complex design bugs before production.
This role is open at our various USA locations, including California, Chicago, Boston, and New York. We are recruiting at all levels, from Engineers (0-4 years) to Leads (5-10 years) and Managers (12-15 years). Join us to work on cutting-edge technologies in a environment that values technical excellence and innovation in the VLSI domain.
This role is open at our various USA locations, including California, Chicago, Boston, and New York. We are recruiting at all levels, from Engineers (0-4 years) to Leads (5-10 years) and Managers (12-15 years). Join us to work on cutting-edge technologies in a environment that values technical excellence and innovation in the VLSI domain.
Key Requirements
B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields.
Graduation date falling between 2012 and 2026.
Expertise in SystemVerilog and UVM (Universal Verification Methodology).
Experience developing testbenches and verification environments from scratch.
Proficiency in scripting with Python, Perl, or TCL.
Hands-on experience with simulation tools like VCS, Xcelium, or Questa.
In-depth knowledge of coverage-driven verification and assertion-based verification.
Strong debugging skills and ability to analyze complex RTL code.
Knowledge of computer architecture and digital logic design fundamentals.
Ability to work effectively within a cross-functional team environment.