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DFT ENGINEER @ TIMES SEMICONDUCTORS

0 Negotiable or Not Mentioned USA 11 days ago GMAIL.COM 430 Views

Join Times Semiconductors as a DFT Engineer and contribute to the reliability and testability of our advanced VLSI designs. You will be involved in implementing Design-for-Test strategies, including Scan, ATPG, and MBIST, ensuring our semiconductor products are manufactured with the highest quality and yield. This role is crucial for bridging the gap between design and high-volume manufacturing.

This opportunity is available at our offices in the USA, specifically in California, Chicago, Boston, and New York. We provide a collaborative platform for engineers to apply their expertise in DFT tools and methodologies to solve complex silicon testing challenges. Whether you are an early-career engineer or a seasoned professional, we invite you to be part of our innovation journey.

Key Requirements

Bachelor's or Master's degree in ECE, EEE, or a similar field. Graduation year range: 2012 to 2026. Strong understanding of DFT fundamentals including Scan and ATPG. Knowledge of MBIST (Memory Built-In Self-Test) and LBIST (Logic BIST). Experience with DFT tools like Tessent, Modus, or Genus. Proficiency in scripting using Python, TCL, or Perl for automation. Understanding of the physical design flow and its impact on DFT. Familiarity with JTAG and boundary scan standards. Strong problem-solving skills for silicon failure analysis and debug. Ability to communicate technical findings effectively with design and manufacturing teams.
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DESIGN VERIFICATION ENGINEER @ TIMES SEMICONDUCTORS

0 Negotiable or Not Mentioned USA 11 days ago GMAIL.COM 248 Views

Become a Design Verification Engineer at Times Semiconductors and ensure the reliability of the next generation of semiconductor products. Your primary responsibility will be to develop and execute comprehensive verification plans using advanced methodologies to ensure design specifications are met perfectly. You will be an essential part of the design cycle, working to identify and resolve complex design bugs before production.

This role is open at our various USA locations, including California, Chicago, Boston, and New York. We are recruiting at all levels, from Engineers (0-4 years) to Leads (5-10 years) and Managers (12-15 years). Join us to work on cutting-edge technologies in a environment that values technical excellence and innovation in the VLSI domain.

Key Requirements

B.E/B.Tech or M.E/M.Tech in ECE/EEE or related fields. Graduation date falling between 2012 and 2026. Expertise in SystemVerilog and UVM (Universal Verification Methodology). Experience developing testbenches and verification environments from scratch. Proficiency in scripting with Python, Perl, or TCL. Hands-on experience with simulation tools like VCS, Xcelium, or Questa. In-depth knowledge of coverage-driven verification and assertion-based verification. Strong debugging skills and ability to analyze complex RTL code. Knowledge of computer architecture and digital logic design fundamentals. Ability to work effectively within a cross-functional team environment.
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RTL DESIGN ENGINEER @ TIMES SEMICONDUCTORS

0 Negotiable or Not Mentioned USA 11 days ago GMAIL.COM 555 Views

Join Times Semiconductors as an RTL Design Engineer to help power the future of VLSI technology. This role involves working on cutting-edge SoC, ASIC, and Analog technologies within a collaborative and innovative environment. You will be responsible for developing high-performance RTL code and ensuring design integrity throughout the development lifecycle for various semiconductor projects.

This position is available at multiple locations across the USA, including California, Chicago, Boston, and New York. We are looking for passionate individuals ranging from entry-level engineers with 0-4 years of experience to seasoned managers with 12-15 years of expertise in the field. This is an excellent opportunity to grow your career in the semiconductor industry with a forward-thinking company.

Key Requirements

Bachelor's or Master's degree in ECE, EEE, or related engineering fields. Graduation year between 2012 and 2026. Strong proficiency in Verilog or SystemVerilog for hardware description. Knowledge of SoC integration processes and methodologies. Experience with scripting languages such as Python, TCL, or Perl. Familiarity with industry-standard EDA tools like VCS, Xcelium, or Questa. Solid understanding of digital logic design and computer architecture. Ability to work in a fast-paced environment on complex ASIC projects. Excellent analytical and problem-solving skills for debugging design issues. Strong communication skills for collaborating with global engineering teams.
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