LAYOUT LEADERSHIP @ SKALEN SEMI
Skalen Semi is seeking an experienced professional for a Layout Leadership role to join our high-impact engineering team. This is a career-accelerating position offering global exposure and deep technical ownership in the semiconductor space. We build engineering teams for companies shaping the future of compute, ranging from stealth-mode silicon product startups to global design services powerhouses. You will be at the forefront of AMS, Memory, and IO layout, working within an environment that values precision and innovation.
In this role, you will lead complex layout projects and mentor engineering talent to ensure the highest standards of silicon design. The ideal candidate finds joy in building hardware at the speed of thought and debugging at the speed of silicon. You will collaborate with global teams to drive leadership growth and deliver next-generation design solutions. This position is perfect for someone looking to take a significant step in their career while working on cutting-edge VLSI and ASIC technologies.
In this role, you will lead complex layout projects and mentor engineering talent to ensure the highest standards of silicon design. The ideal candidate finds joy in building hardware at the speed of thought and debugging at the speed of silicon. You will collaborate with global teams to drive leadership growth and deliver next-generation design solutions. This position is perfect for someone looking to take a significant step in their career while working on cutting-edge VLSI and ASIC technologies.
Key Requirements
Proven experience in AMS, Memory, or IO Layout design.
Demonstrated leadership skills in managing engineering teams.
Extensive knowledge of VLSI and semiconductor manufacturing processes.
Expertise in physical verification tools including DRC and LVS.
Strong understanding of noise analysis and signal integrity issues.
Ability to drive technical ownership and strategic project goals.
Experience working with global design services and product startups.
Proficiency in EDA tools such as Cadence or Synopsys suites.
Excellent communication skills for collaborating with global teams.
Strong debugging skills for silicon and hardware-level issues.