SENIOR PHYSICAL DESIGN ENGINEER (1 POSITION) @ SVENTL
SVENTL is currently seeking a highly skilled Senior Physical Design Engineer to join their innovative team in Bangalore. This role involves working on cutting-edge System-on-Chip (SoC) designs, where the successful candidate will be responsible for driving the full RTL to GDSII implementation process across complex design blocks. As a key member of the engineering team, you will contribute to the development of next-generation technology by ensuring high-performance and power-efficient silicon implementation for advanced projects.
The ideal candidate will possess extensive experience in full-chip and block-level physical design, including expertise in place and route, clock tree synthesis, and static timing analysis. You should be proficient with industry-standard EDA tools such as Fusion Compiler, Innovus, and Primetime. Furthermore, experience with high-speed interfaces like PCIe or CXL is highly desirable, especially when working on advanced power intent and UPF flow integrations to meet rigorous technical specifications.
The ideal candidate will possess extensive experience in full-chip and block-level physical design, including expertise in place and route, clock tree synthesis, and static timing analysis. You should be proficient with industry-standard EDA tools such as Fusion Compiler, Innovus, and Primetime. Furthermore, experience with high-speed interfaces like PCIe or CXL is highly desirable, especially when working on advanced power intent and UPF flow integrations to meet rigorous technical specifications.
Key Requirements
Minimum of 10 years of professional experience in physical design engineering.
Proven expertise in RTL to GDSII implementation for full-chip and block-level designs.
In-depth knowledge of Place and Route (P&R) methodologies.
Demonstrated proficiency in Clock Tree Synthesis (CTS).
Strong understanding of Static Timing Analysis (STA) and timing closure techniques.
Extensive experience with physical verification processes and tools.
Expert-level usage of EDA tools including Fusion Compiler, ICC2, or Innovus.
Professional experience using Primetime for sign-off timing analysis.
Familiarity with RedHawk for power integrity and IR drop analysis.
Strong experience with Power intent (UPF/CPF) and flow integration.
Background in working with high-speed interfaces like PCIe or CXL is preferred.