EMULATION ENGINEER (ZEBU, PALLADIUM, VELOCE) @ SKALEN SEMI
Skalen Semi is actively seeking highly experienced Emulation Engineers specializing in Zebu, Palladium, and Veloce platforms. This role is crucial for supporting large IT and design services clients, as well as fast-growing mid-sized and start-up design services firms. Candidates must possess significant experience, ranging from 6 to 20 years, in ASIC and SoC design environments, focusing on complex verification and emulation flows. The ideal candidate will leverage their deep knowledge of hardware description languages and verification methodologies to ensure successful project delivery and tapeout.
The successful candidate will be involved in high-level digital design, focusing on standard interfaces like PCIe, DDR, Ethernet, and USB, utilizing strong skills in SystemVerilog and UVM. This position is available across multiple key technology hubs in India, including Bangalore, Hyderabad, and Noida. Expertise in EDA tools, semiconductor physics, and relevant IP integration (AXI) is highly valued. This is a chance to contribute significantly to advanced chip design and cutting-edge technology innovations in the AI, ML, and IOT sectors, driving the future of silicon engineering.
The successful candidate will be involved in high-level digital design, focusing on standard interfaces like PCIe, DDR, Ethernet, and USB, utilizing strong skills in SystemVerilog and UVM. This position is available across multiple key technology hubs in India, including Bangalore, Hyderabad, and Noida. Expertise in EDA tools, semiconductor physics, and relevant IP integration (AXI) is highly valued. This is a chance to contribute significantly to advanced chip design and cutting-edge technology innovations in the AI, ML, and IOT sectors, driving the future of silicon engineering.
Key Requirements
6 – 20 Years of experience in Emulation Engineering or related VLSI fields.
Expertise in Synopsys ZeBu, Cadence Palladium, and Siemens Veloce emulation platforms.
Strong proficiency in SystemVerilog and UVM verification methodology.
Experience with RTL Design, complex hardware acceleration, and ASIC/SoC development flows.
In-depth knowledge of standard interfaces including PCIe, DDR, Ethernet, USB, and AXI.
Proven ability to troubleshoot and debug complex hardware/software interaction issues.
Familiarity with digital design principles, electronics engineering, and IC design.
Understanding of C/C++ and Python for scripting, automation, and infrastructure development.
Ability to manage and deliver projects serving large IT clients and fast-growing design services firms.
Must have experience supporting global design teams and collaborating across multiple time zones.