PHYSICAL DESIGN ENGINEERS @ SKALEN SEMI
Skalen Semi is actively seeking highly experienced and motivated Physical Design Engineers to join our growing team. This role is crucial for delivering cutting-edge solutions for our diverse client base, which includes large established IT and design services firms, as well as fast-growing mid-sized and startup design organizations. Successful candidates will be instrumental in executing the full chip physical implementation cycle, ensuring performance, power, and area goals are met on demanding ASIC and SoC projects. The required experience level for this position is between 5 and 15 years, reflecting the complexity and criticality of the tasks involved. The potential work locations for this role are Bangalore, Hyderabad, and Noida.
The responsibilities encompass critical aspects like floor planning, clock tree synthesis, placement and routing, timing closure, and final sign-off verification (DRC/LVS/IR Drop). We are looking for professionals who are proficient in advanced node technology (such as 5nm, 3nm, and 7nm) and skilled in utilizing industry-leading EDA tools like ICC2, Innovus, and FusionCompiler to achieve robust and timely tape-outs. This is an excellent opportunity to contribute to significant projects in the semiconductor industry and collaborate with leading global technology clients.
The responsibilities encompass critical aspects like floor planning, clock tree synthesis, placement and routing, timing closure, and final sign-off verification (DRC/LVS/IR Drop). We are looking for professionals who are proficient in advanced node technology (such as 5nm, 3nm, and 7nm) and skilled in utilizing industry-leading EDA tools like ICC2, Innovus, and FusionCompiler to achieve robust and timely tape-outs. This is an excellent opportunity to contribute to significant projects in the semiconductor industry and collaborate with leading global technology clients.
Key Requirements
Extensive experience (5-15 years) in Physical Design engineering for ASIC/SoC projects.
Expertise in all aspects of physical design flow, including floor planning, power planning, and partitioning.
Proven skills in Placement and Routing techniques for complex digital designs.
Strong understanding and hands-on experience with Clock Tree Synthesis (CTS).
Deep knowledge of static timing analysis (STA), timing closure, and timing constraint management.
Experience with advanced process nodes (e.g., 5nm, 3nm, 7nm).
Proficiency in industry-standard EDA tools such as Synopsys (ICC2, Design Compiler), Cadence (Innovus), or SiemensEDA (FusionCompiler).
Ability to perform comprehensive sign-off checks including DRC, LVS, and IR Drop Analysis.
Familiarity with the complete RTL-to-GDSII flow and Tapeout procedures.
Experience supporting large IT/design services or fast-growing mid-sized/startup design services clients.