LEAD DESIGN VERIFICATION LEAD @ SKALEN SEMI
Skalen Semi is currently seeking a highly experienced Lead Design Verification Lead to join a mid-sized global design services powerhouse. This senior-level role is tailored for professionals with a deep background in the semiconductor industry, specifically focusing on the verification of complex integrated circuits. The successful candidate will be responsible for driving verification strategies and ensuring the functional integrity of cutting-edge silicon designs within a dynamic and collaborative global team environment.
The position requires a mastery of modern verification methodologies and tools. You will be tasked with architecting and developing advanced testbenches, implementing comprehensive verification plans, and leading technical teams through the full verification lifecycle of SoCs, IPs, and subsystems. Based in Bangalore, this role offers the opportunity to work on high-impact projects that define the future of semiconductor technology. Please note that this is a senior leadership position requiring extensive industry experience; applications from interns or freshers are not being accepted at this time.
The position requires a mastery of modern verification methodologies and tools. You will be tasked with architecting and developing advanced testbenches, implementing comprehensive verification plans, and leading technical teams through the full verification lifecycle of SoCs, IPs, and subsystems. Based in Bangalore, this role offers the opportunity to work on high-impact projects that define the future of semiconductor technology. Please note that this is a senior leadership position requiring extensive industry experience; applications from interns or freshers are not being accepted at this time.
Key Requirements
10 to 15 years of professional experience in Design Verification.
Expertise in Functional Verification and RTL Verification techniques.
Advanced proficiency in UVM (Universal Verification Methodology).
Strong command of SystemVerilog for developing complex verification environments.
Proven experience in Testbench Development and Verification Architecture design.
Demonstrated skills in Coverage Driven Verification and Constrained Random Verification.
In-depth knowledge of Assertion Based Verification (SVA) and Scoreboarding.
Extensive experience with SoC, IP, and Subsystem Verification levels.
Proficiency in Debugging, Waveform analysis, and Simulation tools.
Experience with Emulation-ready RTL and Pre-Silicon Validation processes.
Strong leadership skills with the ability to guide senior engineering teams.