DFT LEADERSHIP @ SKALEN SEMI
We are looking for a DFT Leadership expert to join Skalen Semi, where we focus on precision talent for the future of compute. This role provides a unique opportunity for global exposure and the chance to lead technical initiatives in Design for Test (DFT). You will be part of a fast-growing team that supports companies at various stages, from stealth startups to established silicon giants. Your work will directly impact the reliability and testability of next-generation hardware.
As a leader in DFT, you will be responsible for overseeing ATPG, MBIST, and sign-off processes. You will find yourself at home here if you are passionate about waveform debug and silicon bring-up. The role demands a mix of deep technical expertise and the ability to mentor other engineers. By joining Skalen Semi, you are choosing a career path that emphasizes growth, technical excellence, and the ability to work on world-class silicon engineering projects.
As a leader in DFT, you will be responsible for overseeing ATPG, MBIST, and sign-off processes. You will find yourself at home here if you are passionate about waveform debug and silicon bring-up. The role demands a mix of deep technical expertise and the ability to mentor other engineers. By joining Skalen Semi, you are choosing a career path that emphasizes growth, technical excellence, and the ability to work on world-class silicon engineering projects.
Key Requirements
Deep expertise in DFT (Design for Test) methodologies and flows.
Hands-on experience with ATPG and MBIST implementation.
Experience with waveform debug and post-silicon bring-up.
Proven track record in a leadership or managerial capacity.
Knowledge of hardware-software co-design and RTOS environments.
Ability to automate flows using Python or Tcl scripting.
Strong understanding of ASIC/SoC design cycles and sign-off.
Experience in global engineering environments and design services.
Exceptional analytical skills for solving complex silicon problems.
Mentorship experience for developing junior-level DFT engineers.