ETHERNET VERIFICATION ENGINEER @ CADENCE DESIGN SYSTEMS
The role requires significant hands-on experience, specifically between 5 to 10 years, in developing advanced verification environments. Candidates must demonstrate deep expertise in the Ethernet protocol itself, coupled with proficiency in Testbench Development and RTL Verification utilizing modern verification languages and methodologies such as SystemVerilog and UVM. A B.Tech or M.Tech in Electronics and Communication is mandatory for this role.